(1) Field of the Invention
The present invention relates to a semiconductor device, and in particular to a Metal Oxide Semiconductor (MOS) transistor formed in a Silicon-on-Insulator (SOI) substrate.
(2) Description of the Related Art
In recent years, a semiconductor device, in which an N-channel MOS transistor and a P-channel MOS transistor are formed in an SOI substrate, is utilized for various applications. Particularly, a semiconductor device, which adopts a MOS transistor having an offset structure, is used for a drive circuit with a high breakdown voltage.
In fact, in a semiconductor device including plural MOS transistors on a semiconductor substrate, a buffer region is formed between transistors, so that each transistor is not affected by an electrical interference from an adjacent transistor. In addition, an electric potential applied to the buffer region is actually specified to the same electric potential applied to a source of the adjacent MOS transistor, so as to improve the breakdown voltage between a drain and the source in the MOS transistor. The MOS transistor using such method is disclosed for example in Japanese Laid-Open Patent Application No. H11-330383.
Hereafter the exemplified conventional MOS transistor disclosed in Japanese Laid-Open Patent Application No. H11-330383 is described referring to FIG. 1. FIG. 1 is a cross-sectional diagram of a P-channel MOS transistor formed in an SOI substrate.
As shown in FIG. 1, the aforesaid conventional P-channel MOS transistor includes an SOI substrate which has a semiconductor substrate 101, a buried oxide film 102 formed on the semiconductor substrate 101, and a semiconductor layer 103 formed on the buried oxide film 102. The semiconductor layer 103 has an island-like semiconductor layer 103a, of which a P-channel MOS transistor structure is formed, isolated from other elements forming regions by an isolation trench 104. In addition, an I layer with an extremely low concentration impurity, which functions as an intrinsic semiconductor layer substantially, is formed in the region adjacent to the buried oxide film 102 in the semiconductor layer 103. The I layer functions as an electric field alleviation layer.
A drain region 105, which is a P-type impurity layer with a low concentration impurity, is formed in the island-like semiconductor layer 103a. A drain contact region 106, which is a P-type impurity layer with a high concentration impurity, is formed on the surface of the drain region 105, and a drain electrode 106a is placed on the drain contact region 106. In addition, a ring-shaped gate electrode 107 which is made of polycrystalline silicon, and a ring-shaped body region 108, which is an N-type impurity layer with a low concentration impurity, are formed centering on the drain region 105 in the periphery of the drain region 105. A ring-shaped source region 109, which is a P-type impurity layer with a high concentration impurity, and a ring-shaped body contact region 110, which is an N-type impurity layer with a high concentration impurity, are formed in the body region 108.
A source electrode 109a is placed on the source region 109 and the body contact region 110, and the source region 109 and the body region 108 are electrically connected by the source electrode 109a. In addition, a LOCOS oxide film 111 for alleviating electric field concentration is formed in a predetermined part in the island-like semiconductor layer 103a. 
A buffer region 112, which is an N-type impurity layer with a low concentration impurity, is formed in the outer periphery region of the island-like semiconductor layer 103a in other words in the outer periphery region adjacent to the island-like semiconductor layer 103a across the isolation trench 104, so as not to be affected by an electrical interference from the other adjacent elements. A buffer contact layer 113, which is an N-type impurity layer with a high concentration impurity, is formed on the surface of the buffer region 112, and a buffer electrode 113a is placed on the buffer contact layer 113.
Accordingly, the conventional P-channel MOS transistor having the aforesaid structure is characterized in that the drain region 105 is formed in the center of the island-like semiconductor layer 103a, the source region 109 and the body region 108 are formed in the outer periphery of the drain region 105, and a connection unit 114 is placed so as to make the electric potential in the buffer electrode 113a the same as the electric potential in the source electrode 109a. 
FIG. 2 is a drawing showing a part of a potential distribution (dotted and dashed lines) in the case where a high electric potential of positive polarity is applied to the source electrode 109a, while the electric potential of the drain electrode 106a is specified to a ground electric potential in the P-channel MOS transistor having the aforesaid structure. As shown in FIG. 2, a high electric potential of positive polarity with the same electric potential as the source electrode 109a is applied to the buffer electrode 113a through the connection unit 114, so that an electric potential difference between the buffer region 112 and the source region 109 is not generated. Thus an occurrence of an avalanche breakdown between the isolation trench 104 and the source region 109 can be prevented. As a result the breakdown voltage is determined based on the potential distribution in the drain region 105 in the conventional MOS transistor.
FIG. 3 is a drawing showing a part of the potential distribution (dotted and dashed lines) in the case where a high electric potential of positive polarity is applied to the source electrode 109a, while the electric potentials of the buffer electrode 113a and the drain electrode 106a are specified to a ground electric potential in a P-channel MOS transistor without the connection unit 114. In Japanese Laid-Open Patent Application No. H11-330383, it is disclosed that this technology is generally used. However, the body region 108 as the N-type impurity layer is applied with an electric potential which is a higher electric potential than the electric potential of the buffer region 112, so that a depletion layer grows in the body region 108 as the N-type impurity layer. Thus, the breakdown voltage, which is supposed to be determined based on the potential distribution in the drain region 105, is actually determined based on the electric potential concentration generated by a voltage between the drain and the source in the surface region (region A in FIG. 3) between the source region 109 and the isolation trench 104. The electric potential in the surface region (region A) is concentrated and the electric field becomes exceptionally large, so that the electric potential of this case might cause a lowering of the breakdown voltage between the drain and the source in the MOS transistor.
In such a case, a conceivable method is to make the distance between the isolation trench 104 and the source region 109 longer so as to prevent an occurrence of the avalanche breakdown caused by the potential concentration in the surface region (region A in FIG. 3) between the isolation trench 104 and the source region 109. However, there exists a problem that the device area is increased by this method. Thus, it can be expected in the conventional MOS transistor shown in FIG. 1 that the occurrence of the avalanche breakdown in the surface region between the isolation trench 104 and the source region 109 can be prevented without making the distance between the isolation trench 104 and the source region 109 longer, by placing the connection unit 114 for making the potentials of the buffer region 112 and the source region 109 the same, so that the breakdown voltage between the drain and the source can be improved.